MC912DG128A Motorola, MC912DG128A Datasheet - Page 219

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

PA3H–PA0H — 8-Bit Pulse Accumulators Holding Registers
MCCNT — Modulus Down-Counter Count Register
33-ect
MOTOROLA
RESET:
RESET:
$00B6
$00B7
$00B2
$00B3
$00B4
$00B5
BIt 15
BIT 7
BIT 7
Bit 7
BIt 7
BIt 7
Bit 7
Bit 7
1
0
14
6
6
1
6
6
6
6
6
0
PBOVF — Pulse Accumulator B Overflow Flag
Read: any time
Write: has no effect.
These registers are used to latch the value of the corresponding pulse
accumulator when the related bits in register ICPAR ($A8) are enabled
(see
Read or write any time.
A full access for the counter register should take place in one clock cycle.
A separate read/write for high byte and low byte will give different result
than accessing them as a word.
If the RDMCL bit in MCCTL register is cleared, reads of the MCCNT
register will return the present value of the count register. If the RDMCL
This bit is set when the 16-bit pulse accumulator B overflows from
$FFFF to $0000, or when 8-bit pulse accumulator 1 (PAC1) overflows
from $FF to $00.
This bit is cleared by a write to the PBFLG register with bit 1 set.
Any access to the PACN1 and PACN0 registers will clear the PBOVF
flag in this register when TFFCA bit in register TSCR($86) is set.
Pulse
13
5
5
1
5
5
5
5
5
0
Accumulators).
Enhanced Capture Timer
12
4
4
1
4
4
4
4
4
0
11
3
3
1
3
3
3
3
3
0
10
2
2
1
2
2
2
2
2
0
1
9
1
1
MC68HC912DT128A Rev 2.0
1
1
1
1
1
0
Timer Register Descriptions
Enhanced Capture Timer
BIT 0
Bit 8
Bit 0
1
BIT 0
Bit 0
Bit 0
Bit 0
Bit 0
0
$00B6, $00B7
$00B2–$00B5
MCCNTH
MCCNTL
PA3H
PA2H
PA1H
PA0H
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