MC912DG128A Motorola, MC912DG128A Datasheet - Page 297

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

msCAN12 Bus Timing Register 0 (CBTR0)
29-mscan12
MOTOROLA
CBTR0
$0102
RESET
W
R
NOTE:
SJW1
Bit 7
0
WUPM — Wake-Up Mode
CLKSRC — msCAN12 Clock Source
The CMCR1 register can only be written if the SFTRES bit in CMCR0 is
set.
SJW1, SJW0 — Synchronization Jump Width
SJW0
This flag defines whether the integrated low-pass filter is applied to
protect the msCAN12 from spurious wake-ups (see
Wake-Up
This flag defines which clock source the msCAN12 module is driven
from (only for system with CGM module; see
Figure
The synchronization jump width defines the maximum number of time
quanta (Tq) clock cycles by which a bit may be shortened, or
lengthened, to achieve resynchronization on data transitions on the
bus (see
6
0
0 = msCAN12 will wake up the CPU after any recessive to
1 = msCAN12 will wake up the CPU only in case of dominant pulse
0 = The msCAN12 clock source is EXTALi.
1 = The msCAN12 clock source is SYSCLK, twice the frequency of
dominant edge on the CAN bus.
on the bus which has a length of at least approximately T
ECLK.
47).
Table
BRP5
Function).
5
0
MSCAN Controller
41).
BRP4
4
0
BRP3
3
0
Programmer’s Model of Control Registers
BRP2
2
0
MC68HC912DT128A Rev 2.0
Clock
BRP1
System,
Programmable
1
0
MSCAN Controller
BRP0
Bit 0
0
wup
297
.