MC912DG128A Motorola, MC912DG128A Datasheet - Page 316

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

ATD0CTL3/ATD1CTL3 — ATD Control Register 3
Analog-To-Digital Converter (ATD)
MC68HC912DT128A Rev 2.0
316
RESET:
Bit 7
0
0
6
0
0
ASCIF — ATD Sequence Complete Interrupt Flag
S1C — Conversion Sequence Length (Least Significant Bit)
FIFO — Result Register FIFO Mode
Cannot be written in any mode.
Read or write any time.
This control bit works with control bit S8C in ATDCTL5 in determining
how many conversion are performed per sequence. When the S1C bit
is set, a sequence length of 1 is defined. However, if the S8C bit is
also set, the S8C bit takes precedence. For sequence length coding
information see the description for S8C bit in ATDCTL5.
In normal operation, the A/D conversion results map into the result
registers based on the conversion sequence; the result of the first
conversion appears in the first result register, the second result in the
second result register, and so on. In FIFO mode the result register
counter is not reset at the beginning or ending of a conversion
sequence; conversion results are placed in consecutive result
registers between sequences. The result register counter wraps
around when it reaches the end of the result register file. The
conversion counter value in ATDSTAT0 can be used to determine
where in the result register file, the next conversion result will be
placed.
The results register counter is initialized to zero on three events: on
reset, the beginning of a normal (non-FIFO) conversion sequence,
and the end of a normal (non-FIFO) conversion sequence. Therefore,
the reset bit in register ATDTEST1 can be toggled to zero the result
register counter; any sequence allowed to complete normally will zero
0 = No ATD interrupt occurred
1 = ATD sequence complete
0 = result registers do not map to the conversion sequence
1 = result registers map to the conversion sequence
5
0
0
Analog-To-Digital Converter (ATD)
4
0
0
S1C
3
0
FIFO
2
0
FRZ1
1
0
FRZ0
Bit 0
0
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