MC912DG128A Motorola, MC912DG128A Datasheet - Page 149

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

Pseudo-STOP
15-clock
MOTOROLA
Each time the 13-stage counter reaches a count of 4096 XCLK cycles
(every 8192 cycles), a check of the clock monitor status is performed. If
the clock monitor indicates the presence of an external clock limp-home
mode is de-asserted, the LHOME flag is cleared and the limp-home
interrupt flag is set. Upon leaving limp-home mode, BCSP and MCS are
restored to their values before the loss of clock, and all clocks return to
their previous frequencies. If AUTO and BCSP were set before the clock
loss, the SYSCLK ramps-up and the PLL locks at the previously selected
frequency.
To prevent PLL operation when the external clock frequency comes
back, the software should clear the BCSP bit while running in limp-home
mode.
When using an external clock, i.e. a square wave source, it is possible
to exit STOP with the DLY bit cleared. In this case the LHOME flag is
never set and STOP is de-asserted without delay.
Pseudo-STOP is a low power mode similar to STOP where the external
oscillator is allowed to run (at reduced amplitude) whilst the rest of the
part is in STOP. This increases the current consumption over STOP
mode by the amount of current in the oscillator, but reduces wear and
mechanical stress on the crystal.
If the PSTP bit in the PLLCR register is set, the MCU goes into
Pseudo-STOP mode when a STOP instruction is executed.
Pseudo-STOP mode is exited the same as STOP with an external reset,
an external interrupt from IRQ or XIRQ, a Key Wake-Up interrupt from
port J or port H, or an MSCAN Wake-Up interrupt.
The effect of the DLY bit is the same as noted above in
Fast STOP
Recovery.
Clock Functions
Limp-Home and Fast STOP Recovery modes
MC68HC912DT128A Rev 2.0
STOP Exit and
Clock Functions
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