MC912DG128A Motorola, MC912DG128A Datasheet - Page 39

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

SMODN/BKGD/
LSTRB/TAGLO
13-pins
MOTOROLA
MODB/IPIPE1,
MODA/IPIPE0
ADDR[15:8]
DATA[15:8]
ADDR[7:0]
Pin Name
DATA[7:0]
CGMTST
RESET
EXTAL
TAGHI
ECLK
ECLK
XTAL
XIRQ
DBE
CAL
R/W
IRQ
PE6, PE5
Shared
PB[7:0]
PA[7:0]
Table 6 MC68HC912DT128A Signal Description Summary
port
PE7
PE7
PE7
PE6
PE4
PE3
PE2
PE1
PE0
-
-
-
-
Number
112-pin
31–24
64–57
37, 38
Pin
47
48
46
36
36
36
37
39
53
54
55
56
23
Crystal driver and external clock input pins. On reset all the device clocks
are derived from the EXTAL input frequency. XTAL is the crystal output.
An active low bidirectional control signal, RESET acts as an input to
initialize the MCU to a known start-up state, and an output when COP or
clock monitor causes a reset.
External bus pins share function with general-purpose I/O ports A and B.
In single chip modes, the pins can be used for I/O. In expanded modes, the
pins are used for the external buses.
Data bus control and, in expanded mode, enables the drive control of
external buses during external reads.
Inverted E clock used to latch the address.
CAL is the output of the Slow Mode programmable clock divider, SLWCLK,
and is used as a calibration reference for functions such as time of day. It is
overridden when DBE function is enabled. It always has a 50% duty.
Clock generation module test output.
State of mode select pins during reset determine the initial operating mode
of the MCU. After reset, MODB and MODA can be configured as
instruction queue tracking signals IPIPE1 and IPIPE0 or as
general-purpose I/O pins.
E Clock is the output connection for the external bus clock. ECLK is used
as a timing reference and for address demultiplexing.
Low byte strobe (0 = low byte valid), in all modes this pin can be used as
I/O. The low strobe function is the exclusive-NOR of A0 and the internal
SZ8 signal. (The SZ8 internal signal indicates the size 16/8 access.) Pin
function TAGLO used in instruction tagging. See
Indicates direction of data on expansion bus. Shares function with
general-purpose I/O. Read/write in expanded modes.
Maskable interrupt request input provides a means of applying
asynchronous interrupt requests to the MCU. Either falling edge-sensitive
triggering or level-sensitive triggering is program selectable (INTCR
register).
Provides a means of requesting asynchronous nonmaskable interrupt
requests after reset initialization
During reset, this pin determines special or normal operating mode. After
reset, single-wire background interface pin is dedicated to the background
debug function. Pin function TAGHI used in instruction tagging. See
Development
Pinout and Signal Descriptions
Support.
Description
Pinout and Signal Descriptions
MC68HC912DT128A Rev 2.0
Development
Signal Descriptions
Support.
39