MC912DG128A Motorola, MC912DG128A Datasheet - Page 212

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

ICPAR — Input Control Pulse Accumulators Register
MCFLG — 16-Bit Modulus Down-Counter FLAG Register
Enhanced Capture Timer
MC68HC912DT128A Rev 2.0
212
RESET:
RESET:
MCZF
BIT 7
BIT 7
0
0
0
6
0
0
6
0
0
Read: any time
Write: Only for clearing bit 7
MCZF — Modulus Counter Underflow Interrupt Flag
POLF3 – POLF0 — First Input Capture Polarity Status
The 8-bit pulse accumulators PAC3 and PAC2 can be enabled only if
PAEN in PATCL ($A0) is cleared. If PAEN is set, PA3EN and PA2EN
have no effect.
The 8-bit pulse accumulators PAC1 and PAC0 can be enabled only if
PBEN in PBTCL ($B0) is cleared. If PBEN is set, PA1EN and PA0EN
have no effect.
The flag is set when the modulus down-counter reaches $0000.
A write one to this bit clears the flag. Write zero has no effect.
Any access to the MCCNT register will clear the MCZF flag in this
register when TFFCA bit in register TSCR($86) is set.
This are read only bits. Write to these bits has no effect.
Each status bit gives the polarity of the first edge which has caused
an input capture to occur after capture latch has been read.
Each POLFx corresponds to a timer PORTx input.
Read or write any time.
0 = The first input capture has been caused by a falling edge.
1 = The first input capture has been caused by a rising edge.
5
0
0
5
0
0
Enhanced Capture Timer
4
0
0
4
0
0
PA3EN
POLF3
3
0
3
0
POLF2
PA2EN
2
0
2
0
POLF1
PA1EN
1
0
1
0
PA0EN
POLF0
BIT 0
BIT 0
0
0
MOTOROLA
$00A8
$00A7
26-ect