MC912DG128A Motorola, MC912DG128A Datasheet - Page 125

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

11-reset
MOTOROLA
When the CPU begins to service an interrupt, the instruction queue is
cleared, the return address is calculated, and then it and the contents of
the CPU registers are stacked as shown in
After the CCR is stacked, the I bit (and the X bit, if an XIRQ interrupt
service request is pending) is set to prevent other interrupts from
disrupting the interrupt service routine. The interrupt vector for the
highest priority source that was pending at the beginning of the interrupt
sequence is fetched, and execution continues at the referenced location.
At the end of the interrupt service routine, an RTI instruction restores the
content of all registers from information on the stack, and normal
program execution resumes.
If another interrupt is pending at the end of an interrupt service routine,
the register unstacking and restacking is bypassed and the vector of the
interrupt is fetched.
Table 22 Stacking Order on Entry to Interrupts
Resets and Interrupts
Memory Location
SP – 2
SP – 4
SP – 6
SP – 8
SP – 9
CPU Registers
RTN
Table
Y
X
B : A
CCR
H
H
H
MC68HC912DT128A Rev 2.0
: RTN
: Y
: X
22.
L
L
L
Resets and Interrupts
Register Stacking
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