MC912DG128A Motorola, MC912DG128A Datasheet - Page 258

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

Inter-IC Bus
MC68HC912DT128A Rev 2.0
258
NOTE:
To prevent glitches from appearing on the SDA & SCL lines during reset
of the IIC module, set PORTIB bit 6 & 7 to 1 before clearing the IBEN bit.
IBIE — IIC Bus Interrupt Enable
MS/SL — Master/Slave mode select bit
Tx/Rx — Transmit/Receive mode select bit
TXAK — Transmit Acknowledge enable
Upon reset, this bit is cleared. When this bit is changed from 0 to 1, a
START signal is generated on the bus, and the master mode is
selected. When this bit is changed from 1 to 0, a STOP signal is
generated and the operation mode changes from master to slave.
MS/SL is cleared without generating a STOP signal when the master
loses arbitration.
This bit selects the direction of master and slave transfers. When
addressed as a slave this bit should be set by software according to
the SRW bit in the status register. In master mode this bit should be
set according to the type of transfer required. Therefore, for address
cycles, this bit will always be high.
This bit specifies the value driven onto SDA during acknowledge
cycles for both master and slave receivers. Note that values written to
this bit are only used when the IIC is a receiver, not a transmitter.
0 = Interrupts from the IIC module are disabled. Note that this does
1 = Interrupts from the IIC module are enabled. An IIC interrupt
0 = Slave Mode
1 = Master Mode
0 = Receive
1 = Transmit
0 = An acknowledge signal will be sent out to the bus at the 9th
1 = No acknowledge signal response is sent (i.e., acknowledge bit
not clear any currently pending interrupt condition.
occurs provided the IBIF bit in the status register is also set.
clock bit after receiving one byte data
= 1)
Inter-IC Bus
MOTOROLA
12-iicbus