MC912DG128A Motorola, MC912DG128A Datasheet - Page 257

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

IBCR — IIC Bus Control Register
11-iicbus
MOTOROLA
RESET:
IBEN
Bit 7
0
IBIE
6
0
Read and write anytime
IBEN — IIC Bus Enable
IBC5-0
(hex)
This bit controls the software reset of the entire IIC module.
If the IIC module is enabled in the middle of a byte transfer the
interface behaves as follows: slave mode ignores the current transfer
on the bus and starts operating whenever a subsequent start
condition is detected. Master mode will not be aware that the bus is
busy, hence if a start cycle is initiated then the current bus cycle may
become corrupt. This would ultimately result in either the current bus
master or the IIC module losing arbitration, after which bus operation
would return to normal.
1C
1D
1A
1B
1E
1F
17
18
19
0 = The module is reset and disabled. This is the power-on reset
1 = The IIC system is enabled. This bit must be set before any other
MS/SL
5
0
situation. When low the IIC system is held in reset but registers
can still be accessed.
IBCR bits have any effect.
SCL Divider
(clocks)
128
128
144
160
192
240
112
80
96
Tx/Rx
Table 3 IIC Divider and SDA Hold values
4
0
Inter-IC Bus
SDA Hold
(clocks)
TXAK
21
17
17
25
25
33
33
9
9
3
0
RSTA
2
0
IBC5-0
(hex)
3C
3D
3A
3B
3E
3F
37
38
39
MC68HC912DT128A Rev 2.0
1
0
0
SCL Divider
(clocks)
IIC Register Descriptions
1920
1280
1536
1792
2048
2304
2560
3072
3840
IBSWAI
Bit 0
0
Inter-IC Bus
SDA Hold
(clocks)
257
129
129
257
257
385
385
513
513
$00E2
257