MC912DG128A Motorola, MC912DG128A Datasheet - Page 207

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

21-ect
MOTOROLA
PAEN — Pulse Accumulator A System Enable
PAMOD — Pulse Accumulator Mode
PEDGE — Pulse Accumulator Edge Control
PAEN is independent from TEN. With timer disabled, the pulse
accumulator can still function unless pulse accumulator is disabled.
For PAMOD bit = 0 (event counter mode).
For PAMOD bit = 1 (gated time accumulation mode).
If the timer is not active (TEN = 0 in TSCR), there is no divide-by-64
since the E 64 clock is generated by the timer prescaler.
0 = 16-Bit Pulse Accumulator A system disabled. 8-bit PAC3 and
1 = Pulse Accumulator A system enabled. The two 8-bit pulse
0 = event counter mode
1 = gated time accumulation mode
0 = falling edges on PT7 pin cause the count to be incremented
1 = rising edges on PT7 pin cause the count to be incremented
0 = PT7 input pin high enables M divided by 64 clock to Pulse
1 = PT7 input pin low enables M divided by 64 clock to Pulse
PAMOD
PAC2 can be enabled when their related enable bits in ICPACR
($A8) are set.
Pulse Accumulator Input Edge Flag (PAIF) function is disabled.
accumulators PAC3 and PAC2 are cascaded to form the PACA
16-bit pulse accumulator. When PACA in enabled, the PACN3
and PACN2 registers contents are respectively the high and low
byte of the PACA.
PA3EN and PA2EN control bits in ICPACR ($A8) have no effect.
Pulse Accumulator Input Edge Flag (PAIF) function is enabled.
Accumulator and the trailing falling edge on PT7 sets the PAIF
flag.
Accumulator and the trailing rising edge on PT7 sets the PAIF
flag.
0
0
1
1
Enhanced Capture Timer
PEDGE
0
1
0
1
Falling edge
Rising edge
Div. by 64 clock enabled with pin high level
Div. by 64 clock enabled with pin low level
Pin Action
MC68HC912DT128A Rev 2.0
Timer Register Descriptions
Enhanced Capture Timer
207