MC912DG128A Motorola, MC912DG128A Datasheet - Page 97

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

Operation
Bootstrap
Operation
Single-Chip Mode
Normal Operation
Program/Erase
Operation
Programming the Flash EEPROM
5-flash
MOTOROLA
The Flash EEPROM can contain program and data. On reset, it can
operate as a bootstrap memory to provide the CPU with internal
initialization information during the reset sequence.
After reset, the CPU controlling the system will begin booting up by
fetching the first program address from address $FFFE.
The Flash EEPROM allows a byte or aligned word read in one bus cycle.
Misaligned word read require an additional bus cycle. The Flash
EEPROM array responds to read operations only. Write operations are
ignored.
An unprogrammed Flash EEPROM bit has a logic state of one. A bit
must be programmed to change its state from one to zero. Erasing a bit
returns it to a logic one. The Flash EEPROM has a minimum
program/erase life of 100 cycles. Programming or erasing the Flash
EEPROM is accomplished by a series of control register writes.
Programming is restricted to aligned word at a time as determined by
internal signal SZ8 and ADDR[0]. The Flash EEPROM must first be
completely erased prior to programming final data values.
Programming and erasing of Flash locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order shown, other unrelated operations may
occur between the steps. Do not exceed t
Programming the Flash EEPROM is done on a row basis. A row consists
of 64 consecutive bytes starting from addresses $XX00, $XX40, $XX80
Flash EEPROM
FPGM
MC68HC912DT128A Rev 2.0
maximum (40 s).
Flash EEPROM
Operation
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