MC912DG128A Motorola, MC912DG128A Datasheet - Page 195

no-image

MC912DG128A

Manufacturer Part Number
MC912DG128A
Description
Microcontrollers
Manufacturer
Motorola
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC912DG128ACPV
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC912DG128ACPV
Manufacturer:
FREE
Quantity:
20 000
Part Number:
MC912DG128ACPV 5K91D
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
MC912DG128ACPVE
Manufacturer:
MICREL
Quantity:
9 982
Part Number:
MC912DG128ACPVE
Manufacturer:
FREESCALE
Quantity:
1 200
Part Number:
MC912DG128ACPVE
Manufacturer:
FREESCALE
Quantity:
1 970
Part Number:
MC912DG128ACPVE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC912DG128ACPVE
Manufacturer:
FREESCALE
Quantity:
1 970
Part Number:
MC912DG128ACPVER
Manufacturer:
STM
Quantity:
1 244
Part Number:
MC912DG128ACPVER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC912DG128AMPV
Manufacturer:
AD
Quantity:
16
Part Number:
MC912DG128AMPVE
Manufacturer:
FREESCALE
Quantity:
2 902
Part Number:
MC912DG128AVPVE
Quantity:
36
Buffered IC
Channels
9-ect
MOTOROLA
There are two modes of operations for the buffered IC channels.
When enabled (LATQ=1), the main timer value is memorized in the IC
register by a valid input pin transition.
The value of the buffered IC register is latched to its holding register by
the Modulus counter for a given period when the count reaches zero, by
a write $0000 to the modulus counter or by a write to ICLAT in the
MCCTL register.
If the corresponding NOVWx bit of the ICOVW register is cleared, with a
new occurrence of a capture, the contents of IC register are overwritten
by the new value. In case of latching, the contents of its holding register
are overwritten.
If the corresponding NOVWx bit of the ICOVW register is set, the capture
register or its holding register cannot be written by an event unless they
are empty (see
overwritten until it is read or latched in the holding register.
When enabled (LATQ=0), the main timer value is memorized in the IC
register by a valid input pin transition.
If the corresponding NOVWx bit of the ICOVW register is cleared, with a
new occurrence of a capture, the value of the IC register will be transferred
to its holding register and the IC register memorizes the new timer value.
If the corresponding NOVWx bit of the ICOVW register is set, the capture
register or its holding register cannot be written by an event unless they
are empty (see
In queue mode, reads of holding register will latch the corresponding
pulse accumulator value to its holding register.
If the corresponding NOVWx bit of the ICOVW register is set, the
capture register cannot be written unless it is empty.
This will prevent the captured value to be overwritten until it is read.
IC Latch Mode:
IC queue mode:
Enhanced Capture Timer
IC
IC
Channels). This will prevent the captured value to be
Channels).
Enhanced Capture Timer Modes of Operation
MC68HC912DT128A Rev 2.0
Enhanced Capture Timer
195

Related parts for MC912DG128A