MC912DG128A Motorola, MC912DG128A Datasheet - Page 224

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

Block diagram
Serial Communication Interface (SCI)
Multiple Serial Interface
MC68HC912DT128A Rev 2.0
224
MSI
Figure 31 Multiple Serial Interface Block Diagram
Two serial communication interfaces are available on the
MC68HC912DT128A. These are NRZ format (one start, eight or nine
data, and one stop bit) asynchronous communication systems with
independent internal baud rate generation circuitry and SCI transmitters
and receivers. They can be configured for eight or nine data bits (one of
which may be designated as a parity bit, odd or even). If enabled, parity
is generated in hardware for transmitted and received data. Receiver
parity errors are flagged in hardware. The baud rate generator is based
on a modulus counter, allowing flexibility in choosing baud rates. There
is a receiver wake-up feature, an idle line detect feature, a loop-back
mode, and various error detection features. Two port pins for each SCI
provide the external interface for the transmitted data (TXD) and the
received data (RXD).
For a faster wake-up out of WAIT mode by a received SCI message,
both SCI have the capability of sending a receiver interrupt, if enabled,
when RAF (receiver active flag) is set. For compatibility with other
SCI0
SCI1
SPI
Multiple Serial Interface
MOSI/MOMI
MISO/SISO
CS/SS
RxD0
RxD1
TxD0
TxD1
SCK
HC12A4 MSI BLOCK
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
MOTOROLA
2--msi