MC912DG128A Motorola, MC912DG128A Datasheet - Page 178

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

PWEN — PWM Enable
Pulse-Width Modulator
MC68HC912DT128A Rev 2.0
178
RESET:
Bit 7
0
0
6
0
0
Setting any of the PWENx bits causes the associated port P line to
become an output regardless of the state of the associated data
direction register (DDRP) bit. This does not change the state of the data
direction bit. When PWENx returns to zero, the data direction bit controls
I/O direction. On the front end of the PWM channel, the scaler clock is
enabled to the PWM circuit by the PWENx enable bit being high. When
all four PWM channels are disabled, the prescaler counter shuts off to
save power. There is an edge-synchronizing gate circuit to guarantee
that the clock will only be enabled or disabled at an edge.
Read and write anytime.
PWEN3 — PWM Channel 3 Enable
PWEN2 — PWM Channel 2 Enable
PWEN1 — PWM Channel 1 Enable
PWEN0 — PWM Channel 0 Enable
The pulse modulated signal will be available at port P, bit 3 when its
clock source begins its next cycle.
The pulse modulated signal will be available at port P, bit 2 when its
clock source begins its next cycle.
The pulse modulated signal will be available at port P, bit 1 when its
clock source begins its next cycle.
The pulse modulated signal will be available at port P, bit 0 when its
clock source begins its next cycle.
0 = Channel 3 is disabled.
1 = Channel 3 is enabled.
0 = Channel 2 is disabled.
1 = Channel 2 is enabled.
0 = Channel 1 is disabled.
1 = Channel 1 is enabled.
0 = Channel 0 is disabled.
1 = Channel 0 is enabled.
5
0
0
Pulse-Width Modulator
4
0
0
PWEN3
3
0
PWEN2
2
0
PWEN1
1
0
PWEN0
Bit 0
0
MOTOROLA
$0042
8-pwm