MC912DG128A Motorola, MC912DG128A Datasheet - Page 211

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

25-ect
MOTOROLA
ICLAT — Input Capture Force Latch Action
FLMC — Force Load Register into the Modulus Counter Count Register
MCEN — Modulus Down-Counter Enable
MCPR1, MCPR0 — Modulus Counter Prescaler select
When input capture latch mode is enabled (LATQ and BUFEN bit in
ICSYS ($AB) are set), a write one to this bit immediately forces the
contents of the input capture registers TC0 to TC3 and their
corresponding 8-bit pulse accumulators to be latched into the
associated holding registers. The pulse accumulators will be
automatically cleared when the latch action occurs.
Writing zero to this bit has no effect. Read of this bit will return always
zero.
This bit is active only when the modulus down-counter is enabled
(MCEN=1).
A write one into this bit loads the load register into the modulus
counter count register. This also resets the modulus counter
prescaler. Write zero to this bit has no effect.
When MODMC=0, counter starts counting and stops at $0000.
Read of this bit will return always zero.
When MCEN=0, the counter is preset to $FFFF. This will prevent an
early interrupt flag when the modulus down-counter is enabled.
These two bits specify the division rate of the modulus counter
prescaler.
The newly selected prescaler division rate will not be effective until a
load of the load register into the modulus counter count register
occurs.
0 = Modulus counter disabled.
1 = Modulus counter is enabled.
Enhanced Capture Timer
MCPR1
0
0
1
1
MCPR0
0
1
0
1
Prescaler division rate
MC68HC912DT128A Rev 2.0
16
1
4
8
Timer Register Descriptions
Enhanced Capture Timer
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