MC912DG128A Motorola, MC912DG128A Datasheet - Page 38

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

Instruction Queue
Tracking Signals
(IPIPE1 and IPIPE0)
Data Bus Enable
(DBE)
Inverted E clock
(ECLK)
Calibration
reference (CAL)
Clock generation
module
test(CGMTST)
Pinout and Signal Descriptions
MC68HC912DT128A Rev 2.0
38
IPIPE1 (PE6) and IPIPE0 (PE5) signals are used to track the state of the
internal instruction queue. Data movement and execution state
information is time-multiplexed on the two signals. Refer to
Development
The DBE pin (PE7) is an active low signal that will be asserted low during
E-clock high time. DBE provides separation between output of a
multiplexed address and the input of data. When an external address is
stretched, DBE is asserted during what would be the last quarter cycle
of the last E-clock cycle of stretch. In expanded modes this pin is used
to enable the drive control of external buses during external reads. Use
of the DBE is controlled by the NDBE bit in the PEAR register. DBE is
enabled out of reset in expanded modes.
The ECLK pin (PE7) can be used to latch the address for
de-multiplexing. It has the same behavior as the ECLK, except is
inverted. In expanded modes this pin is used to enable the drive control
of external buses during external reads. Use of the ECLK is controlled
by the NDBE and DBENE bits in the PEAR register.
The CAL pin (PE7) is the output of the Slow Mode programmable clock
divider, SLWCLK, and is used as a calibration reference. The SLWCLK
frequency is equal to the crystal frequency out of reset and always has
a 50% duty. If the DBE function is enabled it will override the enabled
CAL output. The CAL pin output is disabled by clearing CALE bit in the
PEAR register.
The CGMTST pin (PE6) is the output of the clocks tested when CGMTE
bit is set in PEAR register. The PIPOE bit must be cleared for the clocks
to be tested
Pinout and Signal Descriptions
Support.
MOTOROLA
12-pins