MC912DG128A Motorola, MC912DG128A Datasheet - Page 230

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

SC0CR2/SC1CR2 — SCI Control Register 2
Multiple Serial Interface
MC68HC912DT128A Rev 2.0
230
RESET:
Bit 7
TIE
0
TCIE
6
0
PE — Parity Enable
PT — Parity Type
Read or write anytime.
TIE — Transmit Interrupt Enable
TCIE — Transmit Complete Interrupt Enable
In the long mode, the SCI circuitry does not begin counting ones in the
search for the idle line condition until a stop bit is received. Therefore,
the last byte’s stop bit and preceding “1” bits do not affect how quickly
an idle line condition can be detected.
If parity is enabled, this bit determines even or odd parity for both the
receiver and the transmitter.
0 = Parity is disabled.
1 = Parity is enabled.
0 = Even parity is selected. An even number of ones in the data
1 = Odd parity is selected. An odd number of ones in the data
0 = TDRE interrupts disabled
1 = SCI interrupt will be requested whenever the TDRE status flag
0 = TC interrupts disabled
1 = SCI interrupt will be requested whenever the TC status flag is
RIE
5
0
character causes the parity bit to be zero and an odd number
of ones causes the parity bit to be one.
character causes the parity bit to be zero and an even number
of ones causes the parity bit to be one.
is set.
set.
Multiple Serial Interface
ILIE
4
0
TE
3
0
RE
2
0
RWU
1
0
Bit 0
SBK
0
$00C3/$00CB
MOTOROLA
8-msi