MC912DG128A Motorola, MC912DG128A Datasheet - Page 253

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

Clock
Synchronization
Handshaking
7-iicbus
MOTOROLA
SCL1
SCL2
SCL
from master to slave mode does not generate a STOP condition.
Meanwhile, a status bit is set by hardware to indicate loss of arbitration.
Since wire-AND logic is performed on SCL line, a high-to-low transition
on SCL line affects all the devices connected on the bus. The devices
start counting their low period and once a device’s clock has gone low,
it holds the SCL line low until the clock high state is reached. However,
the change of low to high in this device clock may not change the state
of the SCL line if another device clock is still within its low period.
Therefore, synchronized clock SCL is held low by the device with the
longest low period. Devices with shorter low periods enter a high wait
state during this time (see
counted off their low period, the synchronized clock SCL line is released
and pulled high. There is then no difference between the device clocks
and the state of the SCL line and all the devices start counting their high
periods. The first device to complete its high period pulls the SCL line low
again.
The clock synchronization mechanism can be used as a handshake in
data transfer. Slave devices may hold the SCL low after completion of
Internal Counter Reset
Figure 39 IIC Clock Synchronization
Inter-IC Bus
Figure
39). When all devices concerned have
WAIT
Start Counting High Period
MC68HC912DT128A Rev 2.0
Inter-IC Bus
IIC Protocol
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