MC912DG128A Motorola, MC912DG128A Datasheet - Page 339

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

INSTRUCTION— BDM Instruction Register (hardware command explanation)
INSTRUCTION -
Hardware
Instruction
Decode
13-dev
MOTOROLA
RESET:
BIT 7
H/F
0
DATA
6
0
SDV — Shifter Data Valid
TRACE — Asserted by the TRACE1 command
CLKSW — Clock Switch
The INSTRUCTION register is written by the BDM hardware as a result
of serial data shifted in on the BKGD pin. It is readable and writable in
Special Peripheral mode on the parallel bus. It is discussed here for two
conditions: when a hardware command is executed and when a
firmware command is executed.
Read and write: all modes
. The hardware clears the INSTRUCTION register if 512 BCLK cycles
occur between falling edges from the host.
The bits in the BDM instruction register have the following meanings
when a hardware command is executed.
Shows that valid data is in the serial interface shift register. Used by
the BDM firmware.
The WRITE_BD_BYTE@FF01 command that changes CLKSW
including 150 cycles after the data portion of the command should be
timed at the old speed. Beginning with the start of the next BDM
command, the new clock can be used for timing BDM
communications.
If ECLK rate is slower than BCLK rate, CLKSW is ignored and BDM
system is forced to operate with ECLK.
0 = No valid data. Shift operation is not complete.
1 = Valid Data. Shift operation is complete.
0 = BDM system operates with BCLK.
1 = BDM system operates with ECLK.
R/W
5
0
Development Support
BKGND
4
0
W/B
3
0
BD/U
2
0
MC68HC912DT128A Rev 2.0
1
0
0
Background Debug Mode
Development Support
BIT 0
0
0
$FF00
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