MC912DG128A Motorola, MC912DG128A Datasheet - Page 260

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

Inter-IC Bus
MC68HC912DT128A Rev 2.0
260
CAUTION:
NOTE:
NOTE:
If, after trying to generate a START signal and neither the IBB nor IBAL
bits are set after several cycles, the IIC should be disabled and
re-enabled with IBEN bit.
IBAL — Arbitration Lost
If, after trying to generate a START signal and neither the IBB nor IBAL
bits are set after several cycles, the IIC should be disabled and
re-enabled with IBEN bit.
SRW — Slave Read/Write
This bit is only valid when the IIC is in slave mode, a complete address
transfer has occurred with an address match and no other transfers have
been initiated.
IBIF — IIC Bus Interrupt Flag
1. SDA sampled as low when the master drives a high during an
2. SDA sampled as a low when the master drives a high during the
3. A start cycle is attempted when the bus is busy.
4. A repeated start cycle is requested in slave mode.
5. A stop condition is detected when the master did not request it.
The arbitration lost bit (IBAL) is set by hardware when the arbitration
procedure is lost. Arbitration is lost in the following circumstances:
This bit must be cleared by software, by writing a one to it.
When IAAS is set this bit indicates the value of the R/W command bit
of the calling address sent from the master.
Checking this bit, the CPU can select slave transmit/receive mode
according to the command of the master.
The IBIF bit is set when an interrupt is pending, which will cause a
processor interrupt request provided IBIE is set. IBIF is set when one
of the following events occurs:
0 = Slave receive, master writing to slave
1 = Slave transmit, master reading from slave
address or data transmit cycle.
acknowledge bit of a data receive cycle.
Inter-IC Bus
MOTOROLA
14-iicbus