MC912DG128A Motorola, MC912DG128A Datasheet - Page 233

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

11-msi
MOTOROLA
RDRF — Receive Data Register Full Flag
IDLE — Idle Line Detected Flag
OR — Overrun Error Flag
NF — Noise Error Flag
FE — Framing Error Flag
Once cleared, IDLE is not set again until the RxD line has been active
and becomes idle again. RDRF is set if a received character is ready
to be read from SCxDR. Clear the RDRF flag by reading SCxSR1 with
RDRF set and then reading SCxDR.
Receiver idle line is detected (the receipt of a minimum of 10/11
consecutive ones). This bit will not be set by the idle line condition
when the RWU bit is set. Once cleared, IDLE will not be set again until
after RDRF has been set (after the line has been active and becomes
idle again).
New byte is ready to be transferred from the receive shift register to
the receive data register and the receive data register is already full
(RDRF bit is set). Data transfer is inhibited until this bit is cleared.
Set during the same cycle as the RDRF bit but not set in the case of
an overrun (OR).
Set when a zero is detected where a stop bit was expected. Clear the
FE flag by reading SCxSR1 with FE set and then reading SCxDR.
0 = SCxDR empty
1 = SCxDR full
0 = RxD line is idle
1 = RxD line is active
0 = No overrun
1 = Overrun detected
0 = Unanimous decision
1 = Noise on a valid start bit, any of the data bits, or on the stop bit
0 = Stop bit detected
1 = Zero detected rather than a stop bit
Multiple Serial Interface
Serial Communication Interface (SCI)
MC68HC912DT128A Rev 2.0
Multiple Serial Interface
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