MC912DG128A Motorola, MC912DG128A Datasheet - Page 90

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

Bus Control and Input/Output
MC68HC912DT128A Rev 2.0
90
RDWE — Read/Write Enable
CALE — Calibration Reference Enable
DBENE — DBE or Inverted E Clock on PE7
TAGLO is a shared function of the PE3/LSTRB pin. In special
expanded modes with LSTRE set and the BDM tagging on, a zero at
the falling edge of E tags the instruction word low byte being read into
the instruction queue.
Normal: write once; Special: write anytime EXCEPT the first time.
Read anytime. This bit has no effect in single-chip modes.
R/W is used for external writes. After reset in normal expanded mode,
it is disabled. If needed it should be enabled before any external
writes.
Read and write anytime.
Normal modes: write once. Special modes: write anytime EXCEPT
the first time. Read anytime.
DBENE controls which signal is output on PE7 when NDBE control bit
is cleared. The inverted E clock output can be used to latch the
address for de-multiplexing. It has the same behavior as the E clock,
except it is inverted. Please note that in the case of idle expansion
bus, the ‘not E clock’ signal could stay high for many cycles.
The DBENE bit has no effect in Single Chip or Peripheral Modes and
PE7 is defaulted to the CAL function if CALE bit is set in PEAR
register or to an I/O otherwise.
0 = PE2 is a general-purpose I/O pin.
1 = PE2 is configured as the R/W pin. In single chip modes, RDWE
0 = Calibration reference is disabled and PE7 is general purpose
1 = Calibration reference is enabled on PE7 in single chip and
0 = PE7 pin used for DBE external control of data enable on
1 = PE7 pin used for inverted E clock output in expanded modes
has no effect and PE2 is a general-purpose I/O pin.
I/O in single chip or peripheral modes or if NDBE bit is set.
peripheral modes or if NDBE bit is set.
memories in expanded modes when NDBE = 0
when NDBE = 0
Bus Control and Input/Output
MOTOROLA
8-bus