MC912DG128A Motorola, MC912DG128A Datasheet - Page 161

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

27-clock
MOTOROLA
MCLK
XCLK
1, 2, 3, 4, 5, 6,...,8190, 8191
1, 2, 3, 4, 5, 6,...,8190, 8191
REGISTER: RTICTL
BIT:RTBYP
MODULUS DIVIDER:
MODULUS DIVIDER:
SC0BD
SC1BD
2048
Figure 19 Clock Chain for SCI0, SCI1, RTI, COP
Bus clock select bits BCSP and BCSS in the clock select register
(CLKSEL) determine which clock drives SYSCLK for the main system
including the CPU and buses. BCSS has no effect if BCSP is set. During
the transition, the clock select output will be held low and all CPU activity
will cease until the transition is complete.
The Module Clock Select bit MCS determines the clock used by the ECT
module and the baud rate generators of the SCIs. In limp-home mode,
the output of MCS is forced to 0, but the MCS bit reads the latched value.
It allows normal operation of the serial and timer subsystems at a fixed
reference frequency while allowing the CPU to operate at a higher,
variable frequency.
16
16
4
BAUD RATE (16x)
BAUD RATE (16x)
BAUD RATE (1x)
BAUD RATE (1x)
TRANSMIT
TRANSMIT
RECEIVE
RECEIVE
Clock Functions
SCI0
SCI0
SCI1
SCI1
REGISTER: RTICTL
BITS: RTR2, RTR1, RTR0
2
2
2
2
2
2
0:1:0
0:0:1
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
0:0:0
TO RTI
BITS: CR2, CR1, CR0
REGISTER: COPCTL
MC68HC912DT128A Rev 2.0
4
4
2
2
4
4
Clock Divider Chains
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
Clock Functions
0:0:0
TO COP
161