MC912DG128A Motorola, MC912DG128A Datasheet - Page 66

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

MODE — Mode Register
Operating Modes
MC68HC912DT128A Rev 2.0
66
RESET:
RESET:
RESET:
RESET:
0
1
1
1
1
0
0
1
The MODE register controls the MCU operating mode and various
configuration options. This register is not in the map in peripheral mode
SMODN, MODB, MODA — Mode Select Special, B and A
ESTR — E Clock Stretch Enable
IVIS — Internal Visibility
These bits show the current operating mode and reflect the status of
the BKGD, MODB and MODA input pins at the rising edge of reset.
Read anytime.
SMODN may only be written if SMODN = 0 (in special modes) but the
first write is ignored.
MODB, MODA may be written once if SMODN = 1; anytime if SMODN
= 0 but the first write is ignored and in special peripheral and reserved
modes cannot be selected.
Determines if the E Clock behaves as a simple free-running clock or
as a bus control signal that is active only for external bus cycles.
ESTR is always one in expanded modes since it is required for
address and data de-multiplexing and must follow stretched cycles.
Normal modes: write once; Special modes: write anytime, read
anytime.
This bit determines whether internal ADDR, DATA, R/W and LSTRB
signals can be seen on the external bus during accesses to internal
locations. In Special Narrow Mode if this bit is set and an internal
access occurs the data will appear wide on Ports A and B. This serves
0 = E never stretches (always free running).
1 = E stretches high during external access cycles and low during
1
0
1
1
non-visible internal accesses (IVIS = 0).
1
1
1
1
Operating Modes
1
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
Normal Single Chip
Special Exp Wide
Normal Exp Wide
Normal Exp Nar
MOTOROLA
$000B
4-modes