MC912DG128A Motorola, MC912DG128A Datasheet - Page 221

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MC912DG128A

Manufacturer Part Number
MC912DG128A
Description
Microcontrollers
Manufacturer
Motorola
Datasheet

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Timer and Modulus Counter Operation in Different Modes
35-ect
MOTOROLA
Read: any time
Write: has no effect.
These registers are used to latch the value of the input capture registers
TC0 – TC3. The corresponding IOSx bits in TIOS ($80) should be
cleared (see
STOP:
BGDM:
WAIT:
NORMAL:
TEN=0:
MCEN=0:
PAEN=1:
PAEN=0:
PBEN=1:
PBEN=0:
IC
Enhanced Capture Timer
Timer and modulus counter are off since clocks are
stopped.
Timer and modulus counter keep on running, unless
TSBCK (REG$86, bit5) is set to one.
Counters keep on running, unless TSWAI in TSCR ($86)
is set to one.
Timer and modulus counter keep on running, unless TEN
in TSCR($86) respectively MCEN in MCCTL ($A6) are
cleared.
All 16-bit timer operations are stopped, can only access
the registers.
Modulus counter is stopped.
16-bit Pulse Accumulator A is active.
8-Bit Pulse Accumulators 3 and 2 can be enabled. (see
ICPAR)
16-bit Pulse Accumulator B is active.
ICPAR)
8-Bit Pulse Accumulators 1 and 0 can be enabled. (see
Channels).
Timer and Modulus Counter Operation in Different Modes
MC68HC912DT128A Rev 2.0
Enhanced Capture Timer
221

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