MC912DG128A Motorola, MC912DG128A Datasheet - Page 234

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

SC0SR2/SC1SR2 — SCI Status Register 2
SC0DRH/SC1DRH — SCI Data Register High
SC0DRL/SC1DRL — SCI Data Register Low
Multiple Serial Interface
MC68HC912DT128A Rev 2.0
234
RESET:
RESET:
RESET:
R7/T7
Bit 7
Bit 7
Bit 7
R8
—
0
—
0
R6/T6
T8
—
—
6
0
0
6
6
PF — Parity Error Flag
Read anytime. Write has no meaning or effect.
RAF — Receiver Active Flag
Indicates if received data’s parity matches parity bit. This feature is
active only when parity is enabled. The type of parity tested for is
determined by the PT (parity type) bit in SCxCR1.
This bit is controlled by the receiver front end. It is set during the RT1
time period of the start bit search. It is cleared when an idle state is
detected or when the receiver circuitry detects a false start bit
(generally due to noise or baud rate mismatch).
If enabled with RIE = 1, RAF set generates an interrupt when
VDDPLL is high while in WAIT mode.
0 = Parity correct
1 = Incorrect parity detected
0 = A character is not being received
1 = A character is being received
R5/T5
—
—
5
0
0
5
0
5
Multiple Serial Interface
R4/T4
—
—
4
0
0
4
0
4
R3/T3
—
—
3
0
0
3
0
3
R2/T2
—
—
2
0
0
2
0
2
R1/T1
—
—
1
0
1
1
0
0
R0/T0
Bit 0
Bit 0
RAF
Bit 0
—
—
0
0
$00C5/$00CD
$00C6/$00CE
$00C7/$00CF
MOTOROLA
12-msi