MC912DG128A Motorola, MC912DG128A Datasheet - Page 154

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

PLLFLG — PLL Flags
Clock Functions
MC68HC912DT128A Rev 2.0
154
RESET:
LOCKIF
Bit 7
0
LOCK
6
0
Read anytime, refer to each bit for write conditions.
LOCKIF — PLL Lock Interrupt Flag
LOCK — Locked Phase Lock Loop Circuit
LHIF — Limp-Home Interrupt Flag
LHOME — Limp-Home Mode Status
To clear the flag, write one to this bit in PLLFLG. Cleared in limp-home
mode.
Regardless of the bandwidth control mode (automatic or manual):
Write has no effect on LOCK bit. This bit is cleared in limp-home mode as
the lock detector cannot operate without the reference frequency.
To clear the flag, write one to this bit in PLLFLG.
For Limp-Home mode, see
modes.
0 = No change in LOCK bit.
1 = LOCK condition has changed, either from a locked state to an
0 = PLL VCO is not within the desired tolerance of the target
1 = After the phase lock loop circuit is turned on, indicates the PLL
0 = No change in LHOME bit.
1 = LHOME condition has changed, either entered or exited
0 = MCU is operating normally, with EXTALi clock available for
1 = Loss of reference clock. CGM delivers PLL VCO limp-home
5
0
0
unlocked state or vice versa.
frequency.
VCO is within the desired tolerance of the target frequency.
limp-home mode.
generating clocks or as PLL reference.
frequency to the MCU.
Clock Functions
4
0
0
3
0
0
Limp-Home and Fast STOP Recovery
2
0
0
LHIF
1
0
LHOME
Bit 0
0
MOTOROLA
$003B
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