MC912DG128A Motorola, MC912DG128A Datasheet - Page 226
MC912DG128A
Manufacturer Part Number
MC912DG128A
Description
Microcontrollers
Manufacturer
Motorola
Datasheet
1.MC912DG128A.pdf
(404 pages)
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SCI Baud Rate
Generation
SCI Register
Descriptions
Multiple Serial Interface
MC68HC912DT128A Rev 2.0
226
The basis of the SCI baud rate generator is a 13-bit modulus counter.
This counter gives the generator the flexibility necessary to achieve a
reasonable level of independence from the CPU operating frequency
and still be able to produce standard baud rates with a minimal amount
of error. The clock source for the generator comes from the M Clock.
Control and data registers for the SCI subsystem are described below.
The memory address indicated for each register is the default address
that is in use after reset. Both SCI have identical control registers
mapped in two blocks of eight bytes.
•
•
•
•
•
A start bit (logic zero), transmitted or received, that indicates the
start of each character.
Data that is transmitted or received least significant bit (LSB) first.
A stop bit (logic one), used to indicate the end of a frame. (A frame
consists of a start bit, a character of eight or nine data bits and a
stop bit.)
A BREAK is defined as the transmission or reception of a logic
zero for one frame or more.
This SCI supports hardware parity for transmit and receive.
SCI Baud Rate
Multiple Serial Interface
Desired
14400
19200
38400
1200
2400
4800
9600
300
600
110
Table 33 Baud Rate Generation
BR Divisor for
M = 4.0 MHz
2273
833
417
208
104
52
26
17
13
—
BR Divisor for
M = 8.0 MHz
4545
2273
833
417
208
104
52
35
26
13
MOTOROLA
4-msi
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