MC912DG128A Motorola, MC912DG128A Datasheet - Page 210

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

MCCTL — 16-Bit Modulus Down-Counter Control Register
Enhanced Capture Timer
MC68HC912DT128A Rev 2.0
210
RESET:
MCZI
BIT 7
NOTE:
0
MODMC
6
0
The two 8-bit pulse accumulators PAC1 and PAC0 are cascaded to form
the PACB 16-bit pulse accumulator. When PACB in enabled, (PBEN=1
in PBCTL, $B0) the PACN1 and PACN0 registers contents are
respectively the high and low byte of the PACB.
When PACN1 overflows from $FF to $00, the Interrupt flag PBOVF in
PBFLG ($B1) is set.
Full count register access should take place in one clock cycle. A
separate read/write for high byte and low byte will give a different result
than accessing them as a word.
Read or write any time.
MCZI — Modulus Counter Underflow Interrupt Enable
MODMC — Modulus Mode Enable
For proper operation, the MCEN bit should be cleared before modifying
the MODMC bit in order to reset the modulus counter to $FF.
RDMCL — Read Modulus Down-Counter Load
0 = Modulus counter interrupt is disabled.
1 = Modulus counter interrupt is enabled.
0 = The counter counts once from the value written to it and will
1 = Modulus mode is enabled. When the counter reaches $0000,
0 = Reads of the modulus count register will return the present
1 = Reads of the modulus count register will return the contents of
RDMCL
5
0
stop at $0000.
the counter is loaded with the latest value written to the
modulus count register.
value of the count register.
the load register.
Enhanced Capture Timer
ICLAT
4
0
FLMC
3
0
MCEN
2
0
MCPR1
1
0
MCPR0
BIT 0
0
MOTOROLA
$00A6
24-ect