MC912DG128A Motorola, MC912DG128A Datasheet - Page 172

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MC912DG128A

Manufacturer Part Number
MC912DG128A
Description
Microcontrollers
Manufacturer
Motorola
Datasheet

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Pulse-Width Modulator
MC68HC912DT128A Rev 2.0
172
(ECLK or Scaled ECLK)
CLOCK SOURCE
PWENx
(CLOCK EDGE SYNC)
GATE
SYNC
Figure 22 Block Diagram of PWM Left-Aligned Output Channel
PPOL = 0
PPOL = 1
possible to know where the count is with respect to the duty value and
software can be used to make adjustments by turning the enable bit off
and on.
The four PWM channel outputs share general-purpose port P pins.
Enabling PWM pins takes precedence over the general-purpose port.
When PWM are not in use, the port pins may be used for discrete input/
output.
RESET
PWCNTx
PWDTY
Pulse-Width Modulator
UP/DOWN
8-BIT COMPARE =
8-BIT COMPARE =
CENTR = 0
PWDTYx
PWPERx
PWPER
S
R
Q
Q
PPOLx
MUX
DATA REGISTER
FROM PORT P
MUX
DRIVER
TO PIN
MOTOROLA
2--pwm

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