MC912DG128A Motorola, MC912DG128A Datasheet - Page 205

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

TFLG2 — Main Timer Interrupt Flag 2
TC2 — Timer Input Capture/Output Compare Register 2
TC3 — Timer Input Capture/Output Compare Register 3
TC0 — Timer Input Capture/Output Compare Register 0
TC1 — Timer Input Capture/Output Compare Register 1
19-ect
MOTOROLA
RESET:
Bit 15
Bit 15
Bit 15
Bit 15
Bit 7
TOF
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
0
14
14
14
14
6
0
0
6
6
6
6
6
6
6
6
TFLG2 indicates when interrupt conditions have occurred. To clear a bit
in the flag register, set the bit to one.
Read anytime. Write used in clearing mechanism (set bits cause
corresponding bits to be cleared).
Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR
register is set.
TOF — Timer Overflow Flag
Set when 16-bit free-running timer overflows from $FFFF to $0000.
This bit is cleared automatically by a write to the TFLG2 register with
bit 7 set. (See also TCRE control bit explanation.)
13
13
13
13
5
0
0
5
5
5
5
5
5
5
5
Enhanced Capture Timer
12
12
12
12
4
0
0
4
4
4
4
4
4
4
4
11
11
11
11
3
0
0
3
3
3
3
3
3
3
3
10
10
10
10
2
0
0
2
2
2
2
2
2
2
2
MC68HC912DT128A Rev 2.0
1
9
1
1
9
1
1
9
1
1
9
1
1
0
0
Timer Register Descriptions
Enhanced Capture Timer
Bit 0
Bit 8
Bit 0
Bit 0
Bit 8
Bit 0
Bit 0
Bit 8
Bit 0
Bit 0
Bit 8
Bit 0
Bit 0
0
0
$0094–$0095
$0096–$0097
$0090–$0091
$0092–$0093
$008F
205