MC912DG128A Motorola, MC912DG128A Datasheet - Page 163

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

Computer Operating Properly (COP)
29-clock
MOTOROLA
PCLK
Figure 21 Clock Chain for MSCAN, SPI, ATD0, ATD1 and BDM
2
2
2
2
2
2
2
2
BITS: SPR2, SPR1, SPR0
REGISTER: SP0BR
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
0:0:0
The COP or watchdog timer is an added check that a program is running
and sequencing properly. When the COP is being used, software is
responsible for keeping a free running watchdog timer from timing out. If
the watchdog timer times out it is an indication that the software is no
longer being executed in the intended sequence; thus a system reset is
initiated. Three control bits allow selection of seven COP time-out
periods. When COP is enabled, sometime during the selected period the
program must write $55 and $AA (in this order) to the COPRST register.
If the program fails to do this the part will reset. If any value other than
$55 or $AA is written, the part is reset.
COUNTER (PR0-PR4)
5-BIT MODULUS
SYSCLK
EXTALi
ECLK
BCLK
BIT RATE
SPI
Clock Functions
SYNCHRONIZER
CLKSRC
CLKSW
LOGIC
BKGD
PIN
2
BKGD DIRECTION
BKGD OUT
BKGD IN
and ATD1
TO ATD0
Computer Operating Properly (COP)
BDM BIT CLOCK:
Receive: Detect falling edge,
count 12 E clocks, Sample input
Transmit 1: Detect falling edge,
count 6 E clocks while output is
high impedance, Drive out 1 E
cycle pulse high, high imped-
ance output again
Transmit 0: Detect falling edge,
Drive out low, count 9 E clocks,
Drive out 1 E cycle pulse high,
high impedance output
MSCAN
CLOCK
MC68HC912DT128A Rev 2.0
Clock Functions
163