MC912DG128A Motorola, MC912DG128A Datasheet - Page 142

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

Clock Functions
MC68HC912DT128A Rev 2.0
142
EXTALi
Clock Monitor Fail
13-stage counter
(Clocked by XCLK)
Limp-Home
BCSP
SYSCLK
Figure 15 Clock Loss during Normal Operation
is forced low. The LHOME flag in the PLLFLG register is set to indicate
that the MCU is running in limp-home mode. A change of this flag sets
the limp-home interrupt flag, LHIF, and if enabled by the LHIE bit, the
limp-home mode interrupt is requested. The Clock Monitor is enabled
irrespective of CME and FCME bit settings. Module clocks to the RTI &
COP (XCLK), BDM (BCLK) and ECT & SCI (MCLK) are forced to be
PCLK (at f
select is unaffected.
The clock monitor is polled each time the 13-stage free running counter
reaches a count of 4096 XCLK cycles i.e. mid-count, hence the clock
status gets checked once every 8192 XCLK cycles. When the presence
of an external clock is detected, the MCU exits limp-home mode,
clearing the LHOME flag and setting the limp-home interrupt flag. Upon
leaving limp-home mode, BCSP and MCS signals are restored to their
values before the clock loss. All clocks return to their normal settings and
Clock Monitor control is returned to the CME & FCME bits. If AUTO and
BCSP bits were set before the clock loss (selecting the PLL to provide a
system clock) the SYSCLK ramps-up and the PLL locks at the previously
selected frequency. To prevent PLL operation when the external clock
0 --> 4096
A
VCOMIN
PLLCLK (Limp-Home)
Clock Functions
) and ECLK is also equal to f
0 --> 4096
B
Restore PLLCLK or EXTALi
Restore BCSP
VCOMIN
.
MSCAN clock
MOTOROLA
8-clock