MC912DG128A Motorola, MC912DG128A Datasheet - Page 255

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

9-iicbus
MOTOROLA
NOTE:
IBC5–IBC0 — IIC Bus Clock Rate 5–0
At 8 MHz system bus frequency, the IIC bus frequency will slow down by
as much as 5%. However, the communications rate of the IIC system will
be automatically adjusted to a slower rate.
This field is used to prescale the clock for bit rate selection. The bit
clock generator is implemented as a prescaled shift register - IBC5-3
select the prescaler divider and IBC2-0 select the shift register tap
point. The IBC bits are decoded to give the Tap and Prescale values
as shown in
The number of clocks from the falling edge of SCL to the first tap
(Tap[1]) is defined by the values shown in the scl2tap column of
Table
shown in the tap2tap column in
generated the SCL period and the SDA Tap is used to determine the
delay from the falling edge of SCL to SDA changing, the SDA hold
time.
The serial bit clock frequency is equal to the CPU clock frequency
divided by the divider shown in
generate the divider values from the IBFD bits is:
IBC2-0
(bin)
000
001
010
011
100
101
110
111
SCL Divider = 2 x ( scl2tap + [ ( SCL_Tap -1 ) x tap2tap ] + 2 )
37, all subsequent tap points are separated by 2
SCL Tap
(clocks)
Table
Table 37 IIC Tap and Prescale Values
10
12
15
5
6
7
8
9
Inter-IC Bus
37.
SDA Tap
(clocks)
1
1
2
2
3
3
4
4
Table
Table
3. The equation used to
37. The SCL Tap is used to
IBC5-3
(bin)
000
001
010
100
101
011
110
111
MC68HC912DT128A Rev 2.0
IIC Register Descriptions
(clocks)
scl2tap
126
14
30
62
4
4
6
6
IBC5-3
Inter-IC Bus
(clocks)
tap2tap
as
128
16
32
64
1
2
4
8
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