MC912DG128A Motorola, MC912DG128A Datasheet - Page 299

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

msCAN12
Receiver Flag
Register (CRFLG)
31-mscan12
MOTOROLA
TSEG13 TSEG12 TSEG11 TSEG10 Time segment 1
0
0
0
0
1
.
.
0
0
0
0
1
.
.
NOTE:
0
0
1
1
1
.
.
TSEG22 – TSEG10 — Time Segment
Time segment 1 (TSEG1) and time segment 2 (TSEG2) are
programmable as shown in
The bit time is determined by the oscillator frequency, the baud rate
prescaler, and the number of time quanta (Tq) clock cycles per bit (as
shown above).
The CBTR1 register can only be written if the SFTRES bit in CMCR0 is
set.
All bits of this register are read and clear only. A flag can be cleared by
writing a 1 to the corresponding bit position. A flag can only be cleared
when the condition which caused the setting is no more valid. Writing a
1. In this case PHASE_SEG1 must be at least 2 TimeQuanta.
Transmit point
Sample point
SYNC_SEG
Time segments within the bit time fix the number of clock cycles per
bit time, and the location of the sample point.
0 = One sample per bit.
1 = Three samples per bit
0
1
0
1
1
.
.
Table 44 Time segment values
16 Tq clock cycles
2 Tq clock cycles
3 Tq clock cycles
4 Tq clock cycles
1 Tq clock cycle
System expects transitions to occur on the bus during this period.
A node in transmit mode will transfer a new value to the CAN bus at
this point.
A node in receive mode will sample the bus at this point. If the three
samples per bit option is selected then this point marks the position
of the third sample.
MSCAN Controller
.
.
Table 43 Time segment syntax
Table
TSEG22 TSEG21 TSEG20 Time segment 2
1
.
0
0
1
.
.
44.
Programmer’s Model of Control Registers
0
0
1
.
.
MC68HC912DT128A Rev 2.0
0
1
1
.
.
MSCAN Controller
2 Tq clock cycles
8 Tq clock cycles
1 Tq clock cycle
.
.
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