MC912DG128A Motorola, MC912DG128A Datasheet - Page 124

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

Central Processing
Unit
Memory
Other Resources
Register Stacking
Resets and Interrupts
MC68HC912DT128A Rev 2.0
124
PEAR register). Out of reset, port J, port H, port K, port IB, port P, port
S, port T, port AD0 and port AD1 are all configured as general-purpose
inputs.
After reset, the CPU fetches a vector from the appropriate address, then
begins executing instructions. The stack pointer and other CPU registers
are indeterminate immediately after reset. The CCR X and I interrupt
mask bits are set to mask any interrupt requests. The S bit is also set to
inhibit the STOP instruction.
After reset, the internal register block is located from $0000 to $03FF,
RAM is at $2000 to $3FFF, and EEPROM is located at $0800 to $0FFF.
In single chip mode one 32-Kbyte FLASH EEPROM module is located
from $4000 to $7FFF and $C000 to $FFFF, and the other three 32-Kbyte
FLASH EEPROM modules are accessible through the program page
window located from $8000 to $BFFF. The first 32-Kbyte FLASH
EEPROM is also accessible through the program page window.
The enhanced capture timer (ECT), pulse width modulation timer
(PWM), serial communications interfaces (SCI0 and SCI1), serial
peripheral interface (SPI), inter-IC bus (IIC), Motorola Scalable CANs
(MSCAN0 and MSCAN1) and analog-to-digital converters (ATD0 and
ATD1) are off after reset.
Once enabled, an interrupt request can be recognized at any time after
the I bit in the CCR is cleared. When an interrupt service request is
recognized, the CPU responds at the completion of the instruction being
executed. Interrupt latency varies according to the number of cycles
required to complete the instruction. Some of the longer instructions can
be interrupted and will resume normally after servicing the interrupt.
Resets and Interrupts
MOTOROLA
10-reset