MC912DG128A Motorola, MC912DG128A Datasheet - Page 168

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

Clock Functions
MC68HC912DT128A Rev 2.0
168
FCMCOP — Force Clock Monitor Reset or COP Watchdog Reset
WCOP — Window COP mode
Writes are not allowed in normal modes, anytime in special modes.
Read anytime.
If DISR is set, this bit has no effect.
Write once in normal modes, anytime in special modes. Read
anytime.
When set, a write to the COPRST register must occur in the last 25%
of the selected period. A premature write will also reset the part. As
long as all writes occur during this window, $55 can be written as often
as desired. Once $AA is written the time-out logic restarts and the
user must wait until the next window before writing to COPRST.
Please note, there is a fixed time uncertainty about the exact COP
counter state when reset, as the initial prescale clock divider in the
RTI section is not cleared when the COP counter is cleared. This
means the effective window is reduced by this uncertainty.
below shows the exact duration of this window for the seven available
COP rates.
0 = Normal operation.
1 = A clock monitor failure reset or a COP failure reset is forced
0 = Normal COP operation
1 = Window COP operation
depending on the state of CME and if COP is enabled.
1. Highest priority interrupt vector is serviced.
CME
0
0
1
1
Clock Functions
COP enabled
0
1
0
1
Clock monitor failure
Forced reset
COP failure
Both
none
(1)
MOTOROLA
Table 27
34-clock