MC912DG128A Motorola, MC912DG128A Datasheet - Page 71

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

INITRG — Initialization of Internal Register Position Register
INITRM — Initialization of Internal RAM Position Register
RAM Mapping
3-mapping
MOTOROLA
RESET:
RESET:
REG15
RAM15
Bit 7
Bit 7
0
0
RAM14
REG14
6
0
6
0
REG[15:11] — Internal register map position
MMSWAI — Memory Mapping Interface Stop in Wait Control
The MC68HC912DT128A has 8K bytes of fully static RAM that is used
for storing instructions, variables, and temporary data during program
execution. Since the RAM is actually implemented with two 4K RAM
arrays, any misaligned word access between last address of first 4K
RAM and first address of second 4K RAM will take two cycles instead of
one. After reset, RAM addressing begins at location $2000 but can be
assigned to any 8K byte boundary within the standard 64K byte address
space. Mapping of internal RAM is controlled by three bits in the INITRM
register.
These bits specify the upper five bits of the 16-bit registers address.
Normal modes: write once; special modes: write anytime. Read
anytime.
This bit controls access to the memory mapping interface when in
Wait mode.
Normal modes: write anytime; special modes: write never. Read
anytime.
0 = Memory mapping interface continues to function during Wait
1 = Memory mapping interface access is shut down during Wait
REG13
RAM13
5
0
5
1
mode.
mode.
Resource Mapping
REG12
4
0
4
0
0
REG11
3
0
3
0
0
2
0
0
2
0
0
MC68HC912DT128A Rev 2.0
1
0
0
1
0
0
Internal Resource Mapping
MMSWAI
Resource Mapping
Bit 0
Bit 0
0
0
0
$0011
$0010
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