MC912DG128A Motorola, MC912DG128A Datasheet - Page 259

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

13-iicbus
MOTOROLA
IBSR — IIC Bus Status Register
RESET:
Bit 7
TCF
1
IAAS
RSTA — Repeat Start
IBSWAI — IIC Stop in WAIT mode
TCF — Data transferring bit
IAAS — Addressed as a slave bit
IBB — IIC Bus busy bit
6
0
Writing a 1 to this bit will generate a repeated START condition on the
bus, provided it is the current bus master. This bit will always be read
as a low. Attempting a repeated start at the wrong time, if the bus is
owned by another master, will result in loss of arbitration.
This status register is read-only with exception of bit 1 (IBIF) and bit 4
(IBAL), which are software clearable
While one byte of data is being transferred, this bit is cleared. It is set
by the falling edge of the 9th clock of a byte transfer.
When its own specific address (IIC Bus Address Register) is matched
with the calling address, this bit is set. The CPU is interrupted
provided the IBIE is set. Then the CPU needs to check the SRW bit
and set its Tx/Rx mode accordingly. Writing to the IIC Bus Control
Register clears this bit.
This bit indicates the status of the bus. When a START signal is
detected, the IBB is set. If a STOP signal is detected, it is cleared.
1 = Generate repeat start cycle
0 = IIC module operates normally
1 = Halt clock generation of IIC module in WAIT mode
0 = Transfer in progress
1 = Transfer complete
0 = Not addressed
1 = Addressed as a slave
0 = Bus is idle
1 = Bus is busy
IBB
5
0
IBAL
Inter-IC Bus
4
0
3
0
0
SRW
2
0
IBIF
1
0
MC68HC912DT128A Rev 2.0
IIC Register Descriptions
RXAK
Bit 0
0
Inter-IC Bus
$00E3
259