MC912DG128A Motorola, MC912DG128A Datasheet - Page 318

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

Analog-To-Digital Converter (ATD)
MC68HC912DT128A Rev 2.0
318
PRS4, PRS3, PRS2, PRS1, PRS0 — Select Divide-By Factor for ATD
P-Clock Prescaler.
1. Maximum conversion frequency is 2 MHz. Maximum P clock divisor value will become
2. Minimum conversion frequency is 500 kHz. Minimum P clock divisor value will become
The binary value written to these bits (1 to 31) selects the divide-by
factor for the modulo counter-based prescaler. The P clock is divided
by this value plus one and then fed into a 2 circuit to generate the
ATD module clock. The divide-by-two circuit insures symmetry of the
output clock signal. Clearing these bits causes the prescale value
default to one which results in a 2 prescale factor. This signal is then
fed into the 2 logic. The reset state divides the P clock by a total of
four and is appropriate for nominal operation at 2 MHz.
shows the divide-by operation and the appropriate range of system
clock frequencies.
Prescale
maximum conversion rate that can be used on this ATD module.
minimum conversion rate that this ATD can perform.
00000
00001
00010
00100
00101
Value
00011
00110
00111
01xxx
1xxxx
Analog-To-Digital Converter (ATD)
Table 50 Final Sample Time Selection
SMP1
Divisor
0
0
1
1
Table 51 Clock Prescaler Values
Total
10
12
14
16
2
4
6
8
SMP0
0
1
0
1
Max P Clock
4 MHz
8 MHz
8 MHz
8 MHz
8 MHz
8 MHz
8 MHz
8 MHz
16 A/D clock periods
Final Sample Time
2 A/D clock periods
4 A/D clock periods
8 A/D clock periods
Do Not Use
(1)
Min P Clock
1 MHz
2 MHz
3 MHz
4 MHz
5 MHz
6 MHz
7 MHz
8 MHz
Table 51
MOTOROLA
(2)
8-atd