MC912DG128A Motorola, MC912DG128A Datasheet - Page 264

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

Post-Transfer
Software
Response
Inter-IC Bus
MC68HC912DT128A Rev 2.0
264
connected to a multi-master bus system, the state of the IIC Bus Busy
bit (IBB) must be tested to check whether the serial bus is free.
If the bus is free (IBB=0), the start condition and the first byte (the slave
address) can be sent. The data written to the data register comprises the
slave calling address and the LSB set to indicate the direction of transfer
required from the slave.
The bus free time (i.e., the time between a STOP condition and the
following START condition) is built into the hardware that generates the
START cycle. Depending on the relative frequencies of the system clock
and the SCL period it may be necessary to wait until the IIC is busy after
writing the calling address to the IBDR before proceeding with the
following instructions. This is illustrated in the following example.
An example of a program which generates the START signal and
transmits the first byte of data (slave address) is shown below:
Transmission or reception of a byte will set the data transferring bit
(TCF) to 1, which indicates one byte communication is finished. The IIC
Bus interrupt bit (IBIF) is set also; an interrupt will be generated if the
interrupt function is enabled during initialization by setting the IBIE bit.
Software must clear the IBIF bit in the interrupt routine first. The TCF bit
will be cleared by reading from the IIC Bus Data I/O Register (IBDR) in
receive mode or writing to IBDR in transmit mode.
Software may service the IIC I/O in the main program by monitoring the
IBIF bit if the interrupt function is disabled. Note that polling should
monitor the IBIF bit rather than the TCF bit since their operation is
different when arbitration is lost.
Note that when an interrupt occurs at the end of the address cycle the
master will always be in transmit mode, i.e. the address is transmitted. If
CHFLAG
TXSTART
IBFREE
BRSET
BSET
MOVB
BRCLR
Inter-IC Bus
IBSR,#$20,*
IBCR,#$30
CALLING,IBDR
IBSR,#$20,*
;WAIT FOR IBB FLAG TO CLEAR
;SET TRANSMIT AND MASTER MODE
;i.e. GENERATE START CONDITION
;TRANSMIT THE CALLING
;ADDRESS, D0=R/W
;WAIT FOR IBB FLAG TO SET
MOTOROLA
18-iicbus