MC912DG128A Motorola, MC912DG128A Datasheet - Page 208

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

PAFLG — Pulse Accumulator A Flag Register
Enhanced Capture Timer
MC68HC912DT128A Rev 2.0
208
RESET:
BIT 7
0
0
6
0
0
CLK1, CLK0 — Clock Select Bits
PAOVI — Pulse Accumulator A Overflow Interrupt enable
PAI — Pulse Accumulator Input Interrupt enable
Read or write anytime. When the TFFCA bit in the TSCR register is set,
any access to the PACNT register will clear all the flags in the PAFLG
register.
PAOVF — Pulse Accumulator A Overflow Flag
If the pulse accumulator is disabled (PAEN = 0), the prescaler clock
from the timer is always used as an input clock to the timer counter.
The change from one selected clock to the other happens
immediately after these bits are written.
Set when the 16-bit pulse accumulator A overflows from $FFFF to
$0000,or when 8-bit pulse accumulator 3 (PAC3) overflows from $FF
to $00.
This bit is cleared automatically by a write to the PAFLG register with
bit 1 set.
0 = interrupt inhibited
1 = interrupt requested if PAOVF is set
0 = interrupt inhibited
1 = interrupt requested if PAIF is set
CLK1
0
0
1
1
5
0
0
Enhanced Capture Timer
CLK0
0
1
0
1
4
0
0
Use timer prescaler clock as timer counter clock
Use PACLK as input to timer counter clock
Use PACLK/256 as timer counter clock frequency
Use PACLK/65536 as timer counter clock
frequency
3
0
0
2
0
0
Clock Source
PAOVF
1
0
BIT 0
PAIF
0
MOTOROLA
$00A1
22-ect