MC912DG128A Motorola, MC912DG128A Datasheet - Page 86

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

PORTE — Port E Register
DDRB — Port B Data Direction Register
Bus Control and Input/Output
MC68HC912DT128A Rev 2.0
86
Function
RESET:
RESET:
Alt. Pin
ECLK or
DDB7
DBE or
Bit 7
BIT 7
PE7
CAL
0
—
IPIPE1 or
MODB or
CGMTST
DDB6
PE6
6
0
—
6
Bits PB[7:0] are associated with addresses ADDR[7:0] and DATA[7:0]
(except in narrow mode) respectively. When this port is not used for
external addresses such as in single-chip mode, these pins can be
used as general-purpose I/O. DDRB determines the primary direction
of each pin. This register is not in the on-chip map in expanded and
peripheral modes. Read and write anytime.
This register determines the primary direction for each port B pin
when functioning as a general-purpose I/O port. DDRB is not in the
on-chip map in expanded and peripheral modes. Read and write
anytime.
This register is associated with external bus control signals and
interrupt inputs, including data bus enable (DBE), mode select
(MODB/IPIPE1, MODA/IPIPE0), E clock, size (LSTRB), read/write
(R/W), IRQ, and XIRQ. When the associated pin is not used for one
of these specific functions, the pin can be used as general-purpose
I/O. The port E assignment register (PEAR) selects the function of
each pin. DDRE determines the primary direction of each port E pin
when configured to be general-purpose I/O.
Some of these pins have software selectable pull-ups (DBE, LSTRB,
R/W, IRQ and XIRQ). A single control bit enables the pull-ups for all
these pins which are configured as inputs.
0 = Associated pin is a high-impedance input
1 = Associated pin is an output
MODA or
DDB5
IPIPE0
PE5
5
0
—
5
Bus Control and Input/Output
DDB4
ECLK
PE4
4
0
—
4
LSTRB or
TAGLO
DDB3
PE3
—
3
0
3
DDB2
R/W
PE2
—
2
0
2
DDB1
PE1
IRQ
—
1
0
1
DDB0
BIT 0
XIRQ
Bit 0
PE0
—
0
MOTOROLA
$0008
$0003
4-bus