MC912DG128A Motorola, MC912DG128A Datasheet - Page 94

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

Flash EEPROM Control Block
Flash EEPROM Arrays
Flash EEPROM
MC68HC912DT128A Rev 2.0
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time is one bus cycle for byte and aligned word access and two bus
cycles for misaligned word operations.
Programming is by aligned word. The Flash EEPROM module supports
bulk erase only.
Each Flash EEPROM module has hardware interlocks which protect
stored data from accidental corruption. An erase- and
program-protected 8-Kbyte block for boot routines is located at the top
of each 32-Kbyte array. Since boot programs must be available at all
times, the only useful boot block is at $E000–$FFFF location. All paged
boot blocks can be used as protected program space if desired.
A 4-byte register block for each module controls the Flash EEPROM
operation. Configuration information is specified and programmed
independently from the contents of the Flash EEPROM array. At reset,
the 4-byte register section starts at address $00F4 and points to the
00FEE32K register block.
After reset, a fixed 32K Flash EEPROM array, 11FEE32K, is located
from addresses $4000 to $7FFF and from $C000 to $FFFF. The other
three 32K Flash EEPROM arrays 00FEE32K, 01FEE32K and
10FEE32K, are mapped through a 16K byte program page window
located from addresses $8000 to $BFFF. The page window has eight
16K byte pages. The last two pages also map the physical location of the
fixed 32K Flash EEPROM array 11FEE32K. In expanded modes, the
Flash EEPROM arrays are turned off. See
Flash EEPROM
Operating
Modes.
MOTOROLA
2--flash