MC912DG128A Motorola, MC912DG128A Datasheet - Page 241

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

19-msi
MOTOROLA
SPE — SPI System Enable
SWOM — Port S Wired-OR Mode
MSTR — SPI Master/Slave Mode Select
CPOL, CPHA — SPI Clock Polarity, Clock Phase
SSOE — Slave Select Output Enable
LSBF — SPI LSB First enable
When MODF is set, SPE always reads zero. SP0CR1 must be written
as part of a mode fault recovery sequence.
Controls not only SPI output pins but also the general-purpose output
pins (PS[4:7]) which are not used by SPI.
When MODF is set, MSTR always reads zero. SP0CR1 must be
written as part of a mode fault recovery sequence.
These two bits are used to specify the clock format to be used in SPI
operations. When the clock polarity bit is cleared and data is not being
transferred, the SCK pin of the master device is low. When CPOL is
set, SCK idles high. See
The SS output feature is enabled only in the master mode by
asserting the SSOE and DDRS7.
Normally data is transferred most significant bit first.This bit does not
affect the position of the MSB and LSB in the data register. Reads and
writes of the data register will always have MSB in bit 7.
0 = SPI internal hardware is initialized and SPI system is in a
1 = PS[4:7] are dedicated to the SPI function
0 = SPI and/or PS[4:7] output buffers operate normally
1 = SPI and/or PS[4:7] output buffers behave as open-drain
0 = Slave mode
1 = Master mode
0 = Data is transferred most significant bit first
1 = Data is transferred least significant bit first
low-power disabled state.
outputs
Multiple Serial Interface
Figure 34
and
Figure
Serial Peripheral Interface (SPI)
MC68HC912DT128A Rev 2.0
35.
Multiple Serial Interface
241