MC912DG128A Motorola, MC912DG128A Datasheet - Page 350

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

Instruction Tagging
Development Support
MC68HC912DT128A Rev 2.0
350
BKEN[1:0], BKDBE, BK1ALE, and BKMBL control how this byte will be
used in the breakpoint comparison.
The instruction queue and cycle-by-cycle CPU activity can be
reconstructed in real time or from trace history that was captured by a
logic analyzer. However, the reconstructed queue cannot be used to
stop the CPU at a specific instruction, because execution has already
begun by the time an operation is visible outside the MCU. A separate
instruction tagging mechanism is provided for this purpose.
Executing the BDM TAGGO command configures two MCU pins for
tagging. The TAGLO signal shares a pin with the LSTRB signal, and the
TAGHI signal shares a pin with the BKGD signal. Tagging information is
latched on the falling edge of ECLK.
Table 64
independently - the state of one pin does not affect the function of the
other. The presence of logic level zero on either pin at the fall of ECLK
performs the indicated function. Tagging is allowed in all modes.
Tagging is disabled when BDM becomes active and BDM serial
commands are not processed while tagging is active.
The tag follows program information as it advances through the queue.
When a tagged instruction reaches the head of the queue, the CPU
enters active background debugging mode rather than execute the
instruction.
shows the functions of the two tagging pins. The pins operate
Development Support
TAGHI
1
1
0
0
Table 64 Tag Pin Function
TAGLO
1
0
1
0
both bytes
high byte
low byte
no tag
Tag
MOTOROLA
24-dev