MC912DG128A Motorola, MC912DG128A Datasheet - Page 266

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

Generation of
Repeated START
Slave Mode
Inter-IC Bus
MC68HC912DT128A Rev 2.0
266
signal must be generated first. The following is an example showing how
a STOP signal is generated by a master receiver.
At the end of data transfer, if the master still wants to communicate on
the bus, it can generate another START signal followed by another slave
address without first generating a STOP signal. A program example is
as shown.
In the slave interrupt service routine, the module addressed as slave bit
(IAAS) should be tested to check if a calling of its own address has just
been received (see
transmit/receive mode select bit (Tx/Rx bit of IBCR) according to the R/
W command bit (SRW). Writing to the IBCR clears the IAAS
automatically. Note that the only time IAAS is read as set is from the
interrupt at the end of the address cycle where an address match
occurred, interrupts resulting from subsequent data transfers will have
IAAS cleared. A data transfer may now be initiated by writing information
to IBDR, for slave transmits, or dummy reading from IBDR, in slave
receive mode. The slave will drive SCL low in-between byte transfers,
SCL is released when the IBDR is accessed in the required mode.
In slave transmitter routine, the received acknowledge bit (RXAK) must
be tested before transmitting the next byte of data. Setting RXAK means
RESTART
MASR
LAMAR
ENMASR
NXMAR
DEC
BEQ
MOVB
DEC
BNE
BSET
BRA
BCLR
MOVB
RTI
BSET
MOVB
Inter-IC Bus
IBCR,#$04
CALLING,IBDR
Figure
RXCNT
ENMASR
RXCNT,D1
D1
NXMAR
IBCR,#$08
NXMAR
IBCR,#$20
IBDR,RXBUF
40). If IAAS is set, software should set the
;DECREASE THE RXCNT
;LAST BYTE TO BE READ
;CHECK SECOND LAST BYTE
;TO BE READ
;NOT LAST OR SECOND LAST
;SECOND LAST, DISABLE ACK
;TRANSMITTING
;LAST ONE, GENERATE ‘STOP’ SIGNAL
;READ DATA AND STORE
ANOTHER START (RESTART)
;TRANSMIT THE CALLING ADDRESS
;D0=R/W
MOTOROLA
20-iicbus