MC912DG128A Motorola, MC912DG128A Datasheet - Page 153

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

PLL Register Descriptions
SYNR — Synthesizer Register
REFDV — Reference Divider Register
CGTFLG — Clock Generator Test Register
19-clock
MOTOROLA
RESET:
RESET:
RESET:
TSTOUT7
Bit 7
Bit 7
Bit 7
0
0
0
0
0
TSTOUT6
6
0
0
6
0
0
6
0
Read anytime, write anytime, except when BCSP = 1 (PLL selected as
bus clock).
If the PLL is on, the count in the loop divider (SYNR) register effectively
multiplies up the bus frequency from the PLL reference frequency by
SYNR + 1. Internally, SYSCLK runs at twice the bus frequency. Caution
should be used not to exceed the maximum rated operating frequency
for the CPU.
Read anytime, write anytime, except when BCSP = 1.
The reference divider bits provides a finer granularity for the PLL
multiplier steps. The reference frequency is divided by REFDV + 1.
Always reads zero, except in test modes.
TSTOUT5
SYN5
5
0
5
0
0
5
0
TSTOUT4
SYN4
Clock Functions
4
0
4
0
0
4
0
TSTOUT3
SYN3
3
0
3
0
0
3
0
Limp-Home and Fast STOP Recovery modes
TSTOUT2
REFDV2
SYN2
2
0
2
0
2
0
TSTOUT1 TSTOUT0
REFDV1
SYN1
MC68HC912DT128A Rev 2.0
1
0
1
0
1
0
REFDV0
SYN0
Bit 0
Bit 0
Bit 0
0
0
0
Clock Functions
$003A
$0038
$0039
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