MC912DG128A Motorola, MC912DG128A Datasheet - Page 218

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

PBFLG — Pulse Accumulator B Flag Register
PBCTL — 16-Bit Pulse Accumulator B Control Register
Enhanced Capture Timer
MC68HC912DT128A Rev 2.0
218
RESET:
RESET:
BIT 7
BIT 7
0
0
0
0
PBEN
6
0
0
6
0
Read or write any time.
16-Bit Pulse Accumulator B (PACB) is formed by cascading the 8-bit
pulse accumulators PAC1 and PAC0.
When PBEN is set, the PACB is enabled. The PACB shares the input pin
with IC0.
PBEN — Pulse Accumulator B System Enable
PBOVI — Pulse Accumulator B Overflow Interrupt enable
Read or write any time.
PBEN is independent from TEN. With timer disabled, the pulse
accumulator can still function unless pulse accumulator is disabled.
0 = 16-bit Pulse Accumulator system disabled. 8-bit PAC1 and
1 = Pulse Accumulator B system enabled. The two 8-bit pulse
0 = interrupt inhibited
1 = interrupt requested if PBOVF is set
5
0
0
5
0
0
PAC0 can be enabled when their related enable bits in
ICPACR ($A8) are set.
accumulators PAC1 and PAC0 are cascaded to form the
PACB 16-bit pulse accumulator. When PACB in enabled, the
PACN1 and PACN0 registers contents are respectively the
high and low byte of the PACB.
PA1EN and PA0EN control bits in ICPACR ($A8) have no
effect.
Enhanced Capture Timer
4
0
0
4
0
0
3
0
0
3
0
0
2
0
0
2
0
0
PBOVF
PBOVI
1
0
1
0
BIT 0
BIT 0
0
0
0
0
MOTOROLA
$00B1
$00B0
32-ect