MC912DG128A Motorola, MC912DG128A Datasheet - Page 256

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

Inter-IC Bus
MC68HC912DT128A Rev 2.0
256
IBC5-0
(hex)
The SDA hold delay is equal to the CPU clock period multiplied by the
SDA Hold value shown in
SDA Hold value from the IBFD bits is:
0A
0B
0C
0D
0E
00
01
02
03
04
05
06
07
08
09
0F
10
12
13
14
15
16
11
SCL Divider
SDA Hold = scl2tap + [ ( SDA_Tap - 1 ) x tap2tap ] + 3
(clocks)
104
20
22
24
26
28
30
34
40
28
32
36
40
44
48
56
68
48
56
64
72
80
88
Table 3 IIC Divider and SDA Hold values
Inter-IC Bus
SDA Hold
(clocks)
10
10
13
13
13
13
17
17
21
11
11
7
7
8
8
9
9
7
7
9
9
9
9
Figure
3. The equation used to generate the
IBC5-0
(hex)
2C
2D
2A
2B
2E
2F
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
SCL Divider
(clocks)
1024
1280
1536
1152
160
192
224
256
288
320
384
480
320
384
448
512
576
640
768
960
640
768
896
MOTOROLA
SDA Hold
(clocks)
129
129
129
129
193
193
257
17
17
33
33
49
49
65
65
33
33
65
65
97
97
65
65
10-iicbus